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Neural Network designs are quite diverse, from VGG-style to ResNet-style, andfrom Convolutional Neural Networks to Transformers. Towards the design ofefficient accelerators, many works have adopted a dataflow-based, inter-layerpipelined architecture, with a customised hardware towards each layer,achieving ultra high throughput and low latency. The deployment of neuralnetworks to such dataflow architecture accelerators is usually hindered by theavailable on-chip memory as it is desirable to preload the weights of neuralnetworks on-chip to maximise the system performance. To address this, networksare usually compressed before the deployment through methods such as pruning,quantization and tensor decomposition. In this paper, a framework for mappingCNNs onto FPGAs based on a novel tensor decomposition method called Mixed-TD isproposed. The proposed method applies layer-specific Singular ValueDecomposition (SVD) and Canonical Polyadic Decomposition (CPD) in a mixedmanner, achieving 1.73x to 10.29x throughput per DSP to state-of-the-art CNNs.Our work is open-sourced: https://github.com/Yu-Zhewen/Mixed-TD

Mixed-TD: Efficient Neural Network Accelerator with Layer-Specific Tensor Decomposition