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Prototyping HPC systems with low-to-mid technology readiness level (TRL)systems is critical for providing feedback to hardware designers, the systemsoftware team (e.g., compiler developers), and early adopters from thescientific community. The typical approach to hardware design and HPC systemprototyping often limits feedback or only allows it at a late stage. In thispaper, we present a set of tools for co-designing HPC systems, called softwaredevelopment vehicles (SDV). We use an innovative RISC-V design as ademonstrator, which includes a scalar CPU and a vector processing unit capableof operating large vectors up to 16 kbits. We provide an incrementalmethodology and early tangible evidence of the co-design process that providefeedback to improve both architecture and system software at a very early stageof system development.

Software Development Vehicles to enable extended and early co-design: a RISC-V and HPC case of study