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On-chip analog Ising Machines (IMs) are a promising means to solve difficultcombinatorial optimization problems. For scalable on-chip realizations to bepractical, 1) the problem should map scalably to Ising form, 2)interconnectivity between spins should be sparse, 3) the number of bits ofcoupling resolution (BCR) needed for programming interconnection weights shouldbe small, and 4) the chip should be capable of solving problems with differentconnection topologies. We explore these issues for the SATisfiability problemand devise FPIM, a reconfigurable on-chip analog Ising machine scheme wellsuited for SAT. To map SAT problems onto FPIMs, we leverage Boolean logicsynthesis as a first step, but replace synthesized logic gates with Isingequivalent circuits whose analog dynamics solve SAT by minimizing the IsingHamiltonian. We apply our approach to 2000 benchmark problems fromSATLIB,demonstrating excellent scaling, together with low sparsity and low BCRthat are independent of problem scale. Placement/routing reveals a veryfeasible requirement of less than 10 routing tracks to implement all thebenchmarks, translating to an area requirement of about 10mm^2 for aprogrammable 1000-spin FPIM in 65nm technology.

FPIM: Field-Programmable Ising Machines for Solving SAT