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Enabling On-Device Learning (ODL) for Ultra-Low-Power Micro-Controller Units(MCUs) is a key step for post-deployment adaptation and fine-tuning of DeepNeural Network (DNN) models in future TinyML applications. This paper tacklesthis challenge by introducing a novel reduced precision optimization techniquefor ODL primitives on MCU-class devices, leveraging the State-of-Artadvancements in RISC-V RV32 architectures with support for vectorized 16-bitfloating-point (FP16) Single-Instruction Multiple-Data (SIMD) operations. Ourapproach for the Forward and Backward steps of the Back-Propagation trainingalgorithm is composed of specialized shape transform operators and MatrixMultiplication (MM) kernels, accelerated with parallelization and loopunrolling. When evaluated on a single training step of a 2D Convolution layer,the SIMD-optimized FP16 primitives result up to 1.72$\times$ faster than theFP32 baseline on a RISC-V-based 8+1-core MCU. An average computing efficiencyof 3.11 Multiply and Accumulate operations per clock cycle (MAC/clk) and 0.81MAC/clk is measured for the end-to-end training tasks of a ResNet8 and a DS-CNNfor Image Classification and Keyword Spotting, respectively -- requiring 17.1ms and 6.4 ms on the target platform to compute a training step on a singlesample. Overall, our approach results more than two orders of magnitude fasterthan existing ODL software frameworks for single-core MCUs and outperforms by1.6 $\times$ previous FP32 parallel implementations on a Continual Learningsetup.

Reduced Precision Floating-Point Optimization for Deep Neural Network On-Device Learning on MicroControllers