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As large language models (LLMs) like ChatGPT exhibited unprecedented machineintelligence, it also shows great performance in assisting hardware engineersto realize higher-efficiency logic design via natural language interaction. Toestimate the potential of the hardware design process assisted by LLMs, thiswork attempts to demonstrate an automated design environment that explores LLMsto generate hardware logic designs from natural language specifications. Torealize a more accessible and efficient chip development flow, we present ascalable four-stage zero-code logic design framework based on LLMs withoutretraining or finetuning. At first, the demo, ChipGPT, begins by generatingprompts for the LLM, which then produces initial Verilog programs. Second, anoutput manager corrects and optimizes these programs before collecting theminto the final design space. Eventually, ChipGPT will search through this spaceto select the optimal design under the target metrics. The evaluation shedssome light on whether LLMs can generate correct and complete hardware logicdesigns described by natural language for some specifications. It is shown thatChipGPT improves programmability, and controllability, and shows broader designoptimization space compared to prior work and native LLMs alone.

ChipGPT: How far are we from natural language hardware design