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Field-Programmable Gate Array (FPGA)-based Software-Defined Radio (SDR) iswell-suited for experimenting with advanced wireless communication systems, asit allows to alter the architecture promptly while obtaining high performance.However, programming the FPGA using a Hardware Description Language (HDL) is atime-consuming task for FPGA developers and difficult for software developers,which limits the potential of SDR. High-Level Synthesis (HLS) tools aid thedesigners by allowing them to program on a higher layer of abstraction.However, if not carefully designed, it may lead to a degradation in computingperformance or significant increase in resource utilization. This work showsthat it is feasible to design modern Orthogonal Frequency Division Multiplex(OFDM) baseband processing modules like channel estimation and equalizationusing HLS without sacrificing performance and to integrate them in an HDLdesign to form a fully-operational FPGA-based Wi-Fi (IEEE 802.11a/g/n)transceiver. Starting from no HLS experience, a design with minor overhead interms of latency and resource utilization as compared to the HDL approach wascreated in less than one month. We show the readability of the sequential logicas coded in HLS, and discuss the lessons learned from the approach taken andthe benefits it brings for further design and experimentation. The FPGA designgenerated by HLS was verified to be bit-true with its MATLAB implementation insimulation. Furthermore, we show its practical performance when deployed on aSystem-on-Chip (SoC)-based SDR using a professional wireless connectivitytester.

Accelerating FPGA-Based Wi-Fi Transceiver Design and Prototyping by High-Level Synthesis