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The advancement of Deep Learning (DL) is driven by efficient Deep NeuralNetwork (DNN) design and new hardware accelerators. Current DNN design isprimarily tailored for general-purpose use and deployment on commerciallyviable platforms. Inference at the edge requires low latency, compact andpower-efficient models, and must be cost-effective. Digital processors based ontypical von Neumann architectures are not conducive to edge AI given the largeamounts of required data movement in and out of memory. Conversely,analog/mixed signal in-memory computing hardware accelerators can easilytranscend the memory wall of von Neuman architectures when acceleratinginference workloads. They offer increased area and power efficiency, which areparamount in edge resource-constrained environments. In this paper, we proposeAnalogNAS, a framework for automated DNN design targeting deployment on analogIn-Memory Computing (IMC) inference accelerators. We conduct extensive hardwaresimulations to demonstrate the performance of AnalogNAS on State-Of-The-Art(SOTA) models in terms of accuracy and deployment efficiency on various TinyMachine Learning (TinyML) tasks. We also present experimental results that showAnalogNAS models achieving higher accuracy than SOTA models when implemented ona 64-core IMC chip based on Phase Change Memory (PCM). The AnalogNAS searchcode is released: https://github.com/IBM/analog-nas

AnalogNAS: A Neural Network Design Framework for Accurate Inference with Analog In-Memory Computing