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Memory disaggregation has emerged as an alternative to traditional serverarchitecture in data centers. This paper introduces DRackSim, a simulationinfrastructure to model rack-scale hardware disaggregated memory. DRackSimmodels multiple compute nodes, memory pools, and a rack-scale interconnectsimilar to GenZ. An application-level simulation approach simulates an x86out-of-order multi-core processor with a multi-level cache hierarchy at computenodes. A queue-based simulation is used to model a remote memory controller andrack-level interconnect, which allows both cache-based and page-based access toremote memory. DRackSim models a central memory manager to manage address spaceat the memory pools. We integrate community-accepted DRAMSim2 to perform memorysimulation at local and remote memory using multiple DRAMSim2 instances. Anincremental approach is followed to validate the core and cache subsystem ofDRackSim with that of Gem5. We measure the performance of various HPC workloadsand show the performance impact for different nodes/pools configuration.

DRackSim: Simulator for Rack-scale Memory Disaggregation