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Leakage contracts have recently been proposed as a new security abstractionat the Instruction Set Architecture (ISA) level. Such contracts aim tofaithfully capture the information processors may leak through side effects oftheir microarchitectural implementations. However, so far, we lack averification methodology to check that a processor actually satisfies a givenleakage contract. In this paper, we address this problem by developing LeaVe,the first tool for verifying register-transfer-level (RTL) processor designsagainst ISA-level leakage contracts. To this end, we introduce a decouplingtheorem that separates security and functional correctness concerns whenverifying contract satisfaction. LeaVe leverages this decoupling to makeverification of contract satisfaction practical. To scale to realisticprocessor designs LeaVe further employs inductive reasoning on relationalabstractions. Using LeaVe, we precisely characterize the side-channel securityguarantees provided by three open-source RISC-V processors, thereby obtainingthe first contract satisfaction proofs for RTL processor designs.

Specification and Verification of Side-channel Security for Open-source Processors via Leakage Contracts