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Over the past decade, polar codes have received significant traction and havebeen selected as the coding method for the control channel in fifth-generation(5G) wireless communication systems. However, conventional polar codes arereliant solely on binary (2x2) kernels, which restricts their block length tobeing only powers of 2. In response, multi-kernel (MK) polar codes have beenproposed as a viable solution to attain greater code length flexibility. Thispaper proposes an unrolled architecture for encoding both systematic andnon-systematic MK polar codes, capable of high-throughput encoding of codesconstructed with binary, ternary (3x3), or binary-ternary mixed kernels. Theproposed scheme exhibits an unprecedented level of flexibility by supporting 83different codes and offering various architectures that provide trade-offsbetween throughput and resource consumption. The FPGA implementation resultsdemonstrate that a partially-pipelined polar encoder of size N=4096 operatingat a frequency of 270 MHz gives a throughput of 1080 Gbps. Additionally, a newcompiler implemented in Python is given to automatically generate HDL modulesfor the desired encoders. By inserting the desired parameters, a designer cansimply obtain all the necessary VHDL files for FPGA implementation.

Unrolled Architectures for High-Throughput Encoding of Multi-Kernel Polar Codes