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This paper introduces a novel simulation tool for analyzing and trainingneural network models tailored for compute-in-memory hardware. The toolleverages physics-based device models to enable the design of neural networkmodels and their parameters that are more hardware-accurate. The initial studyfocused on modeling a CMOS-based floating-gate transistor and memristor deviceusing measurement data from a fabricated device. Additionally, the toolincorporates hardware constraints, such as the dynamic range of dataconverters, and allows users to specify circuit-level constraints. A case studyusing the MNIST dataset and LeNet-5 architecture demonstrates the tool'scapability to estimate area, power, and accuracy. The results showcase thepotential of the proposed tool to optimize neural network models forcompute-in-memory hardware.

Modeling and Analysis of Analog Non-Volatile Devices for Compute-In-Memory Applications