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Fabrication errors pose a significant challenge in scaling up solid-statequantum devices to the sizes required for fault-tolerant (FT) quantumapplications. To mitigate the resource overhead caused by fabrication errors,we combine two approaches: (1) leveraging the flexibility of a modulararchitecture, (2) adapting the procedure of quantum error correction (QEC) toaccount for fabrication defects. We simulate the surface code adapted to qubitarrays with arbitrarily distributed defects to find metrics that characterizehow defects affect fidelity. We then determine the impact of defects on theresource overhead of realizing a fault-tolerant quantum computer, on achiplet-based modular architecture. Our strategy for dealing with fabricationdefects demonstrates an exponential suppression of logical failure where errorrates of non-faulty physical qubits are ~0.1% in a circuit-based noise model.This is a typical regime where we imagine running the defect-free surface code.We use our numerical results to establish post-selection criteria for buildinga device from defective chiplets. Using our criteria, we then evaluate theresource overhead in terms of the average number of fabricated physical qubitsper logical qubit. We find that an optimal choice of chiplet size, based on thedefect rate and target fidelity, is essential to limiting any additional errorcorrection overhead due to defects. When the optimal chiplet size is chosen, ata defect rate of 1% the resource overhead can be reduced to below 3X and 6Xrespectively for the two defect models we use, for a wide range of targetperformance. We also determine cutoff fidelity values that help identifywhether a qubit should be disabled or kept as part of the error correctioncode.

Codesign of quantum error-correcting codes and modular chiplets in the presence of defects