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Metal inter-layer via (MIV) in Monolithic three-dimensional integratedcircuits (M3D-IC) is used to connect inter-layer devices and provide power andclock signals across multiple layers. The size of MIV is comparable to logicgates because of the significant reduction in substrate layers due tosequential integration. Despite MIV's small size, the impact of MIV on theperformance of adjacent devices should be considered to implement IC designs inM3D-IC technology. In this work, we systematically study the changes inperformance of transistors when they are placed near MIV to understand theeffect of MIV on adjacent devices when MIV passes through the substrate.Simulation results suggest that the keep-out-zone (KOZ) for MIV should beconsidered to ensure the reliability of M3D-IC technology and this KOZ ishighly dependent on the M3D-IC process. In this paper, we show that thetransistor placed near MIV considering the M1 metal pitch as the separationwill have up to $68,668\times$ increase in leakage current, when the channeldoping is $10^{15} cm^{-3}$, source/drain doping of $10^{18}cm^{-3}$ andsubstrate layer height of $100\ nm$. We also show that, this increase inleakage current can also be reduced significantly by having KOZ around MIV,which is dependent on the process.

Metal Inter-layer Via Keep-out-zone in M3D IC: A Critical Process-aware Design Consideration