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Data movement costs constitute a significant bottleneck in modern machinelearning (ML) systems. When combined with the computational complexity ofalgorithms, such as neural networks, designing hardware accelerators with lowenergy footprint remains challenging. Finite state automata (FSA) constitute atype of computation model used as a low-complexity learning unit in ML systems.The implementation of FSA consists of a number of memory states. However, FSAcan be in one of the states at a given time. It switches to another state basedon the present state and input to the FSA. Due to its natural synergy withmemory, it is a promising candidate for in-memory computing for reduced datamovement costs. This work focuses on a novel FSA implementation using resistiveRAM (ReRAM) for state storage in series with a CMOS transistor for biasingcontrols. We propose using multi-level ReRAM technology capable oftransitioning between states depending on bias pulse amplitude and duration. Weuse an asynchronous control circuit for writing each ReRAM-transistor cell forthe on-demand switching of the FSA. We investigate the impact of thedevice-to-device and cycle-to-cycle variations on the cell and show that FSAtransitions can be seamlessly achieved without degradation of performance.Through extensive experimental evaluation, we demonstrate the implementation ofFSA on 1T1R ReRAM crossbar.

Finite State Automata Design using 1T1R ReRAM Crossbar