English (United Kingdom)

https://curated-unify.zendy.io/wp-json/zendy-region/v1/featured_content/oa?rat=en

https://curated-unify.zendy.io/wp-json/zendy-region/v1/highlighted_journal/

Global: Zendy Plus annual

Presents the access of premium content as premium feature

Premium Content

Presents the keyphrase highlighting as premium feature

Keyphrase Highlighting

Presents the summarisation as premium feature

Summarisation

Insights

Presents the pdf analysis as premium feature

PDF Analysis

Presents the zaia usage as premium feature

ZAIA

Global: Zendy Plus monthly

Global: Zendy Tools annual

Global: Zendy Tools monthly

Global: Zendy Free Plan

In a typical RTL to GDSII flow, floorplanning or macro placement is acritical step in achieving decent quality of results (QoR). Moreover, intoday's physical synthesis flows (e.g., Synopsys Fusion Compiler or CadenceGenus iSpatial), a floorplan .def with macro and IO pin placements is typicallyneeded as an input to the front-end physical synthesis. Recently, with theincreasing complexity of IP blocks, and in particular with auto-generated RTLfor machine learning (ML) accelerators, the number of hard macros in a singleRTL block can easily run into the several hundreds. This makes the task ofgenerating an automatic floorplan (.def) with IO pin and macro placements forfront-end physical synthesis even more critical and challenging. The so-calledperipheral approach of forcing macros to the periphery of the layout is nolonger viable when the ratio of the sum of the macro perimeters to thefloorplan perimeter is large, since this increases the required stacking depthof macros. In this paper, we develop a novel multilevel physical planningapproach that exploits the hierarchy and dataflow inherent in the design RTL,and describe its realization in a new hierarchical macro placer, Hier-RTLMP.Hier-RTLMP borrows from traditional approaches used in manual system-on-chip(SoC) floorplanning to create an automatic macro placement for use with largeIP blocks containing very large numbers of hard macros. Empirical studiesdemonstrate substantial improvements over the previous RTL-MP macro placementapproach, and promising post-route improvements relative to a leadingcommercial place-and-route tool.

Hier-RTLMP: A Hierarchical Automatic Macro Placer for Large-scale Complex IP Blocks