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The current work explores a geometrically engineered dual gate GaAs nanowireFET with state of the art miniaturized dimensions for high performance chargequbit operation at room temperature. Relevant gate voltages in such device cancreate two voltage tunable quantum dots (VTQDs) underneath the gates, as wellas can manipulate their eigenstate detuning and the inter-dot coupling togenerate superposition, whereas a small drain bias may cause its collapseleading to qubit read out. Such qubit operations, i.e., Initialization,Manipulation, and Measurement, are theoretically modeled in the present work bydeveloping a second quantization filed operator based Schrodinger-Poissonself-consistent framework coupled to non-equilibrium Greens function formalism.The study shows that the Bloch sphere coverage can be discretized along polarand azimuthal directions by reducing the nanowire diameter and increasing theinter-dot separation respectively, that can be utilized for selectiveinformation encoding. The theoretically obtained stability diagrams suggestthat downscaled nanowire diameter and increased gate separation sharpen thebonding and anti-bonding states with reduced anticrossing leading to a gradualtransformation of the hyperbolic current mapping into a pair of straight lines.However, the dephasing time in the proposed GaAs VTQD-based qubit may besignificantly improved by scaling down both the nanowire diameter and gateseparation. Therefore, the present study suggests an optimization window forgeometrical engineering of a dual gate nanowire FET qubit to achieve superiorqubit performance. Most importantly, such device is compatible with themainstream CMOS technology and can be utilized for large scale implementationby little modification of the state of the art fabrication processes.

Design aspects of dual gate GaAs nanowire FET for room temperature charge qubit operation: A study on diameter and gate engineering