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Caches are used to reduce the speed differential between the CPU and memoryto improve the performance of modern processors. However, attackers can usecontention-based cache timing attacks to steal sensitive information fromvictim processes through carefully designed cache eviction sets. And L1 datacache attacks are widely exploited and pose a significant privacy andconfidentiality threat. Existing hardware-based countermeasures mainly focus oncache partitioning, randomization, and cache line flushing, which unfortunatelyeither incur high overhead or can be circumvented by sophisticated attacks. Inthis paper, we propose a novel hardware-software co-design called BackCachewith the idea of always achieving cache hits instead of cache misses tomitigate contention-based cache timing attacks on the L1 data cache. BackCacheplaces the evicted cache lines from the L1 data cache into a fully-associativebackup cache to hide the evictions. To improve the security of BackCache, weintroduce a randomly used replacement policy (RURP) and a dynamic backup cacheresizing mechanism. We also present a theoretical security analysis todemonstrate the effectiveness of BackCache. Our evaluation on the gem5simulator shows that BackCache can degrade the performance by 1.33%, 7.34%, and7.59% For OS kernel, single-thread, and multi-thread benchmarks.

BackCache: Mitigating Contention-Based Cache Timing Attacks by Hiding Cache Line Evictions