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Recent works have introduced task-based parallelization schemes to accelerategraph search and sparse data-structure traversal, where some solutions scale upto thousands of processing units (PUs) on a single chip. However parallelizingthese memory-intensive workloads across millions of cores requires a scalablecommunication scheme as well as designing a cost-efficient computing node thatmakes multi-node systems practical, which have not been addressed in previousresearch. To address these challenges, we propose a task-oriented scalablechiplet architecture for distributed execution (Tascade), a multi-node systemdesign that we evaluate with up to 256 distributed chips -- over a million PUs.We introduce an execution model that scales to this level via proxy regions andselective cascading, which reduce overall communication and improve loadbalancing. In addition, package-time reconfiguration of our chiplet-baseddesign enables creating chip products that optimized post-silicon for differenttarget metrics, such as time-to-solution, energy, or cost. We evaluate sixapplications and four datasets, with several configurations and memorytechnologies to provide a detailed analysis of the performance, power, and costof data-centric execution at a massive scale. Our parallelization ofBreadth-First-Search with RMAT-26 across a million PUs -- the largest of theliterature -- reaches 3021 GTEPS.

Massive Data-Centric Parallelism in the Chiplet Era