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We investigate die-level and wafer-scale uniformity of Dolan-bridge andbridgeless Manhattan Josephson junctions, using multiple substrates with andwithout through-silicon vias (TSVs). Dolan junctions fabricated on planarsubstrates have the highest yield and lowest room-temperature conductancespread, equivalent to ~100 MHz in transmon frequency. In TSV-integratedsubstrates, Dolan junctions suffer most in both yield and disorder, makingManhattan junctions preferable. Manhattan junctions show pronounced conductancedecrease from wafer centre to edge, which we qualitatively capture using ageometric model of spatially-dependent resist shadowing during junctionelectrode evaporation. Analysis of actual junction overlap areas using scanningelectron micrographs supports the model, and further points to a remnantspatial dependence possibly due to contact resistance.

Wafer-scale uniformity of Dolan-bridge and bridgeless Manhattan-style Josephson junctions for superconducting quantum processors