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The continued need for improvements in accuracy, throughput, and efficiencyof Deep Neural Networks has resulted in a multitude of methods that make themost of custom architectures on FPGAs. These include the creation ofhand-crafted networks and the use of quantization and pruning to reduceextraneous network parameters. However, with the potential of static solutionsalready well exploited, we propose to shift the focus to using the varyingdifficulty of individual data samples to further improve efficiency and reduceaverage compute for classification. Input-dependent computation allows for thenetwork to make runtime decisions to finish a task early if the result meets aconfidence threshold. Early-Exit network architectures have become anincreasingly popular way to implement such behaviour in software.  We create: A Toolflow for Hardware Early-Exit Network Automation (ATHEENA),an automated FPGA toolflow that leverages the probability of samples exitingearly from such networks to scale the resources allocated to different sectionsof the network. The toolflow uses the data-flow model of fpgaConvNet, extendedto support Early-Exit networks as well as Design Space Exploration to optimizethe generated streaming architecture hardware with the goal of increasingthroughput/reducing area while maintaining accuracy. Experimental results onthree different networks demonstrate a throughput increase of $2.00\times$ to$2.78\times$ compared to an optimized baseline network implementation with noearly exits. Additionally, the toolflow can achieve a throughput matching thesame baseline with as low as $46\%$ of the resources the baseline requires.

ATHEENA: A Toolflow for Hardware Early-Exit Network Automation