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3D FPGAs have recently been produced as the next generation of the FPGAfamily to continue the integration of more transistors on a single chipseamlessly. In this paper, we propose a complete CAD flow to implement anarbitrary logic circuit on the 3D FPGA. The partitioning and placement stagesof the flow are based on the simulated annealing algorithm. Furthermore, therouting stage is a modified version of the Pathfinder algorithm. The simulationresults indicate that the comparison between 2D FPGA and 3D FPGA (including2-tier) shows that the circuit speed increases by 28.66% and minimum channelwidth decrease by 29.92%, while the total area raises by 8.86%. Finally, theresults of the comparison between 2-tier and 4-tier in 3D FPGA show thatcircuit speed and minimum channel width increase by 15.95% and 15.92% in4-tier, respectively. Meanwhile, the total area increases only by 1.96%.

Implementation of Digital Circuits on Three-Dimensional FPGAs Using Simulated Annealing