English (United Kingdom)

https://curated-unify.zendy.io/wp-json/zendy-region/v1/featured_content/oa?rat=en

https://curated-unify.zendy.io/wp-json/zendy-region/v1/highlighted_journal/

Global: Zendy Tools annual

Presents the keyphrase highlighting as premium feature

Keyphrase Highlighting

Presents the summarisation as premium feature

Summarisation

Insights

Presents the pdf analysis as premium feature

PDF Analysis

Presents the zaia usage as premium feature

ZAIA

Global: Zendy Tools monthly

Global: Zendy Plus monthly

Presents the access of premium content as premium feature

Premium Content

Global: Zendy Plus annual

Global: Zendy Free Plan

An important aspect that strongly impacts the experimental feasibility ofquantum circuits is the ratio of gate times and typical error time scales.Algorithms with circuit depths that significantly exceed the error time scaleswill result in faulty quantum states and error correction is inevitable. Wepresent a comparison of the theoretical minimal gate time, i.e., the quantumspeed limit (QSL), for realistic two- and multi-qubit gate implementations inneutral atoms and superconducting qubits. Subsequent to finding the QSLs forindividual gates by means of optimal control theory we use them to quantify thecircuit QSL of the quantum Fourier transform and the quantum approximateoptimization algorithm. In particular, we analyze these quantum algorithms interms of circuit run times and gate counts both in the standard gate model andthe parity mapping. We find that neutral atom and superconducting qubitplatforms show comparable weighted circuit QSLs with respect to the systemsize.

Comparing planar quantum computing platforms at the quantum speed limit