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Memory optimization for deep neural network (DNN) inference gains highrelevance with the emergence of TinyML, which refers to the deployment of DNNinference tasks on tiny, low-power microcontrollers. Applications such as audiokeyword detection or radar-based gesture recognition are heavily constrained bythe limited memory on such tiny devices because DNN inference requires largeintermediate run-time buffers to store activations and other intermediate data,which leads to high memory usage. In this paper, we propose a new FusedDepthwise Tiling (FDT) method for the memory optimization of DNNs, which,compared to existing tiling methods, reduces memory usage without inducing anyrun time overhead. FDT applies to a larger variety of network layers thanexisting tiling methods that focus on convolutions. It improves TinyML memoryoptimization significantly by reducing memory of models where this was notpossible before and additionally providing alternative design points for modelsthat show high run time overhead with existing methods. In order to identifythe best tiling configuration, an end-to-end flow with a new path discoverymethod is proposed, which applies FDT and existing tiling methods in a fullyautomated way, including the scheduling of the operations and planning of thelayout of buffers in memory. Out of seven evaluated models, FDT achievedsignificant memory reduction for two models by 76.2% and 18.1% where existingtiling methods could not be applied. Two other models showed a significant runtime overhead with existing methods and FDT provided alternative design pointswith no overhead but reduced memory savings.

Fused Depthwise Tiling for Memory Optimization in TinyML Deep Neural Network Inference