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To accommodate the growing memory footprints of today's applications, CPUvendors have employed large DRAM caches, backed by large non-volatile memorieslike Intel Optane (e.g., Intel's Cascade Lake). The existing computerarchitecture simulators do not provide support to model and evaluate systemswhich use DRAM devices as a cache to the non-volatile main memory. In thiswork, we present a cycle-level DRAM cache model which is integrated with gem5.This model leverages the flexibility of gem5's memory devices models and fullsystem support to enable exploration of many different DRAM cache designs. Wedemonstrate the usefulness of this new tool by exploring the design space of aDRAM cache controller through several case studies including the impact ofscheduling policies, required buffering, combining different memorytechnologies (e.g., HBM, DDR3/4/5, 3DXPoint, High latency) as the cache andmain memory, and the effect of wear-leveling when DRAM cache is backed by NVMmain memory. We also perform experiments with real workloads in full-systemsimulations to validate the proposed model and show the sensitivity of theseworkloads to the DRAM cache sizes.

A Cycle-level Unified DRAM Cache Controller Model for 3DXPoint Memory Systems in gem5