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Graph Neural Network (GNN) inference is used in many real-world applications.Data sparsity in GNN inference, including sparsity in the input graph and theGNN model, offer opportunities to further speed up inference. Also, manypruning techniques have been proposed for model compression that increase thedata sparsity of GNNs. We propose Dynasparse, a comprehensive hardware-softwarecodesign on FPGA to accelerate GNN inference through dynamic sparsityexploitation. For this, we decouple the GNN computation kernels from the basiccomputation primitives, and explore hardware-software codesign as follows: 1)Hardware design: We propose a novel unified accelerator design on FPGA toefficiently execute various computation primitives. We develop a customizedsoft processor that is tightly coupled with the accelerator to execute aruntime system. Moreover, we develop efficient hardware mechanisms to profilethe data sparsity and perform on-the-fly data format transformation to preparethe input data for various computation primitives; 2) Software design: Wedevelop a runtime system that works synergistically with the accelerator toperform dynamic kernel-to-primitive mapping based on data sparsity. Weimplement Dynasparse on a state-of-the-art FPGA platform, Xilinx Alveo U250,and evaluate the design using widely used GNN models (GCN, GraphSAGE, GIN andSGC). For the above GNN models and various input graphs, the proposedaccelerator and dynamic kernel-to-primitive mapping reduces the inferencelatency by $3.73\times$ on the average compared with the static mappingstrategies employed in the state-of-the-art GNN accelerators. Compared withstate-of-the-art CPU (GPU) implementations, Dynasparse achieves up to$56.9\times$ ($2.37\times$) speedup in end-to-end latency.

Dynasparse: Accelerating GNN Inference through Dynamic Sparsity Exploitation