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Benefiting from performance advantages under short code lengths, polar codesare well-suited for certain scenarios, such as the future Internet of Things(IoT) applications that require high reliability and low power. Existing listflip decoders can efficiently further enhance the error-correction performanceof polar codes with finite code lengths, particularly the dynamic successivecancellation list flip (D-SCLF) decoder with flexible high-ordererror-correction capability (FHECC). However, to the best of our knowledge,current list flip decoders cannot effectively balance complexity anderror-correction efficiency. To address this, we propose a parity-check-aidedD-SCLF (PC-DSCLF) decoder. This decoder, based on FHECC and the characteristicsof the list flip decoding process, introduces a simplified flip metric and ahybrid check scheme, along with a decoding method that supports the checkscheme, enabling it to retain FHECC while achieving low complexity. Simulationresults show that the proposed PC-DSCLF decoder achieves up to a 51.1\% averagecomplexity reduction compared to the D-SCLF algorithm with distributed CRC for$PC(512, 256+24)$

Balanced Low-Complexity and Flexible Error-Correction List Flip Decoding for Polar Codes