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SoCs are now designed with their own AI accelerator segment to accommodatethe ever-increasing demand of Deep Learning (DL) applications. With powerfulMAC engines for matrix multiplications, these accelerators show high computingperformance. However, because of limited memory resources (i.e., bandwidth andcapacity), they fail to achieve optimum system performance during large batchtraining and inference. In this work, we propose a memory system with highon-chip capacity and bandwidth to shift the gear of AI accelerators frommemory-bound to achieving system-level peak performance. We develop the memorysystem with DTCO-enabled customized SOT-MRAM as large on-chip memory throughSTCO and detailed characterization of the DL workloads. %We evaluate ourworkload-aware memory system on the CV and NLP benchmarks and observesignificant PPA improvement compared to an SRAM-based in both inference andtraining modes. Our workload-aware memory system achieves 8X energy and 9Xlatency improvement on Computer Vision (CV) benchmarks in training and 8Xenergy and 4.5X latency improvement on Natural Language Processing (NLP)benchmarks in training while consuming only around 50% of SRAM area atiso-capacity.

System and Design Technology Co-optimization of SOT-MRAM for High-Performance AI Accelerator Memory System