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Reverse engineering of FPGA based designs from the flattened LUT levelnetlist to high level RTL helps in verification of the design or inunderstanding legacy designs. We focus on flattened netlists for FPGA devicesfrom Xilinx 7 series and Zynq 7000. We propose a design element groupingalgorithm that makes use of the location information of the elements on thephysical device after place and route. The proposed grouping algorithm givesclusters with average NMI of 0.73 for groupings including all element types.The benchmarks chosen include a range of designs from communication, arithmeticunits, processors and DSP processing units.

Word-Level Structure Identification In FPGA Designs Using Cell Proximity Information