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Millimeter wave (mmW) codesigned 802.11ad-based joint radar communication(JRC) systems have been identified as a potential solution for realizing highbandwidth connected vehicles for next-generation intelligent transportationsystems. The radar functionality within the JRC enables accurate detection andlocalization of mobile targets, which can significantly speed up the selectionof the optimal high-directional narrow beam required for mmW communicationsbetween the base station and mobile target. To bring JRC to reality, a radarsignal processing (RSP) accelerator, co-located with the wireless communicationphysical layer (PHY), on edge platforms is desired. In this work, we discussthe three-dimensional digital hardware RSP framework for 802.11ad-based JRC todetect the range, azimuth, and Doppler velocity of multiple targets. We presenta novel efficient reconfigurable architecture for RSP on multi-processorsystem-on-chip (MPSoC) via hardware-software co-design, word-lengthoptimization, and serial-parallel configurations. We demonstrate the functionalcorrectness of the proposed fixed-point architecture and significant savings inresource utilization (~40-70), execution time (1.5x improvement), and powerconsumption (50%) over floating-point architecture. The acceleration onhardware offers a 120-factor improvement in execution time over the benchmarkQuad-core processor. The proposed architecture enables on-the-flyreconfigurability to support different azimuth precision and Doppler velocityresolution, offering a real-time trade-off between functional accuracy anddetection time. We demonstrate end-to-end RSP on MPSoC with a user-friendlygraphical user interface (GUI).

Hardware Software Co-Design Based Reconfigurable Radar Signal Processing Accelerator for Joint Radar-Communication System