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Weak memory models allow for simplified hardware and increased performance inthe memory hierarchy at the cost of increased software complexity. In weakmemory models, explicit synchronization is needed to enforce ordering betweendifferent processors. Acquire and release semantics provide a powerfulprimitive for expressing only the ordering required for correctness. In thisproject, we explore adding load-acquire and store-release instructions to theRISC-V ISA. We add support to the herd formal memory model, the gem5cycle-approximate simulator, and the LLVM/Clang toolchain. Because theseinstructions do not exist in the RISC-V standard, there is an inherent urgencyto ratify explicit load-acquire/store-release instructions in order to preventmultiple ABI implementations and ecosystem fragmentation. We found that forworkloads with a high degree of sharing and heavy contention, the impact ofless memory ordering is muted, but our changes successfully encode thesemantics we desire.

Adding Explicit Load-Acquire and Store-Release Instructions to the RISC-V ISA