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Virtualization is a key technology used in a wide range of applications, fromcloud computing to embedded systems. Over the last few years, mainstreamcomputer architectures were extended with hardware virtualization support,giving rise to a set of virtualization technologies (e.g., Intel VT, Arm VE)that are now proliferating in modern processors and SoCs. In this article, wedescribe our work on hardware virtualization support in the RISC-V CVA6 core.Our contribution is multifold and encompasses architecture, microarchitecture,and design space exploration. In particular, we highlight the design of a setof microarchitectural enhancements (i.e., G-Stage Translation Lookaside Buffer(GTLB), L2 TLB) to alleviate the virtualization performance overhead. We alsoperform a Design Space Exploration (DSE) and accompanying post-layoutsimulations (based on 22nm FDX technology) to assess Performance, Power ,andArea (PPA). Further, we map design variants on an FPGA platform (Genesys 2) toassess the functional performance-area trade-off. Based on the DSE, we selectan optimal design point for the CVA6 with hardware virtualization support. Forthis optimal hardware configuration, we collected functional performanceresults by running the MiBench benchmark on Linux atop Bao hypervisor for asingle-core configuration. We observed a performance speedup of up to 16%(approx. 12.5% on average) compared with virtualization-aware non-optimizeddesign at the minimal cost of 0.78% in area and 0.33% in power. Finally, allwork described in this article is publicly available and open-sourced for thecommunity to further evaluate additional design configurations and softwarestacks.

CVA6 RISC-V Virtualization: Architecture, Microarchitecture, and Design Space Exploration