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The domain wall-magnetic tunnel junction (DW-MTJ) is a versatile device thatcan simultaneously store data and perform computations. These three-terminaldevices are promising for digital logic due to their nonvolatility, low-energyoperation, and radiation hardness. Here, we augment the DW-MTJ logic gate withvoltage controlled magnetic anisotropy (VCMA) to improve the reliability oflogical concatenation in the presence of realistic process variations. VCMAcreates potential wells that allow for reliable and repeatable localization ofdomain walls. The DW-MTJ logic gate supports different fanouts, allowing formultiple inputs and outputs for a single device without affecting area. Wesimulate a systolic array of DW-MTJ Multiply-Accumulate (MAC) units with 4-bitand 8-bit precision, which uses the nonvolatility of DW-MTJ logic gates toenable fine-grained pipelining and high parallelism. The DW-MTJ systolic arrayprovides comparable throughput and efficiency to state-of-the-art CMOS systolicarrays while being radiation-hard. These results improve the feasibility ofusing domain wall-based processors, especially for extreme-environmentapplications such as space.

Parallel Matrix Multiplication Using Voltage Controlled Magnetic Anisotropy Domain Wall Logic