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Dynamic digital timing analysis is a promising alternative to analogsimulations for verifying particularly timing-critical parts of a circuit. Anecessary prerequisite is a digital delay model, which allows to accuratelypredict the input-to-output delay of a given transition in the input signal(s)of a gate. Since all existing digital delay models for dynamic digital timinganalysis are deterministic, however, they cannot cover delay fluctuationscaused by PVT variations, aging and analog signal noise. The only exceptionknown to us is the $\eta$-IDM introduced by F\"ugger et al. at DATE'18, whichallows to add (very) small adversarially chosen delay variations to thedeterministic involution delay model, without endangering its faithfulness. Inthis paper, we show that it is possible to extend the range of allowed delayvariations so significantly that realistic PVT variations and aging are coveredby the resulting extended $\eta$-IDM.

A Digital Delay Model Supporting Large Adversarial Delay Variations