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The ever-increasing size and computational complexity of today'smachine-learning algorithms pose an increasing strain on the underlyinghardware. In this light, novel and dedicated architectural solutions arerequired to optimize energy efficiency by leveraging opportunities (such asintrinsic parallelism and robustness to quantization errors) exposed byalgorithms. We herein address this challenge by introducing a flexibletwo-stages computing pipeline. The pipeline can support fine-grained operandquantization through software-supported Single Instruction Multiple Data (SIMD)operations. Moreover, it can efficiently execute sequential multiplicationsover SIMD sub-words thanks to zero-skipping and Canonical Signed Digit (CSD)coding. Finally, a lightweight repacking unit allows changing the bitwidth ofsub-words at run-time dynamically. These features are implemented within atight energy and area budget. Indeed, experimental results showcase that ourapproach greatly outperforms traditional hardware SIMD ones both in terms ofarea and energy requirements. In particular, our pipeline occupies up to 53.1%smaller than a hardware SIMD one supporting the same sub-word widths, whileperforming multiplication up to 88.8% more efficiently.

A Soft SIMD Based Energy Efficient Computing Microarchitecture