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Iterative solutions of sparse linear systems and sparse eigenvalue problemshave a fundamental role in vital fields of scientific research and engineering.The crucial computing kernel for such iterative solutions is the multiplicationof a sparse matrix by a dense vector. Efficient implementation of sparsematrix-vector multiplication (SpMV) and linear solvers are therefore essentialand has been subjected to extensive research across a variety of computingarchitectures and accelerators such as central processing units (CPUs),graphical processing units (GPUs), many integrated cores (MICs), and fieldprogrammable gate arrays (FPGAs). Unleashing the full potential of anarchitecture/accelerator requires determining the factors that affect anefficient implementation of SpMV. This article presents the first of its kind,in-depth survey covering over two hundred state-of-the-art optimization schemesfor solving sparse iterative linear systems with a focus on computing SpMV. Anew taxonomy for iterative solutions and SpMV techniques common to allarchitectures is proposed. This article includes reviews of SpMV techniques forall architectures to consolidate a single taxonomy to encouragecross-architectural and heterogeneous-architecture developments. However, theprimary focus is on GPUs. The major contributions as well as the primary,secondary, and tertiary contributions of the SpMV techniques are firsthighlighted utilizing the taxonomy and then qualitatively compared. A summaryof the current state of the research for each architecture is discussedseparately. Finally, several open problems and key challenges for futureresearch directions are outlined.

Performance Enhancement Strategies for Sparse Matrix-Vector Multiplication (SpMV) and Iterative Linear Solvers