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Performing data-intensive tasks in the von Neumann architecture ischallenging to achieve both high performance and power efficiency due to thememory wall bottleneck. Computing-in-memory (CiM) is a promising mitigationapproach by enabling parallel in-situ multiply-accumulate (MAC) operationswithin the memory with support from the peripheral interface and datapath.SRAM-based charge-domain CiM (CD-CiM) has shown its potential of enhanced powerefficiency and computing accuracy. However, existing SRAM-based CD-CiM facesscaling challenges to meet the throughput requirement of high-performancemulti-bit-quantization applications. This paper presents an SRAM-basedhigh-throughput ReLU-optimized CD-CiM macro. It is capable of completing MACand ReLU of two signed 8b vectors in one CiM cycle with only one A/Dconversion. Along with non-linearity compensation for the analog computing andA/D conversion interfaces, this work achieves 51.2GOPS throughput and10.3TOPS/W energy efficiency, while showing 88.6% accuracy in the CIFAR-10dataset.

A 65nm 8b-Activation 8b-Weight SRAM-Based Charge-Domain  Computing-in-Memory Macro Using A Fully-Parallel Analog Adder Network and A  Single-ADC Interface