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We investigate iterative low-resolution message-passing algorithms forquasi-cyclic LDPC codes with horizontal and vertical layered schedules. Coarsequantization and layered scheduling are highly relevant for hardwareimplementations to reduce the bit width of messages and the number of decodingiterations. As a novelty, this paper compares the two scheduling variants incombination with mutual information maximizing compression operations invariable and check nodes. We evaluate the complexity and error rate performancefor various configurations. Dedicated hardware architectures for regularquasi-cyclic LDPC decoders are derived on a conceptual level. Thehardware-resource estimates confirm that most of the complexity lies within therouting network operations. Our simulations reveal similar error rateperformance for both layered schedules but a slightly lower average iterationcount for the horizontal decoder.

Low-Resolution Horizontal and Vertical Layered Mutual Information Maximizing LDPC Decoding