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The demand for computation resources and energy efficiency of ConvolutionalNeural Networks (CNN) applications requires a new paradigm to overcome the"Memory Wall". Analog In-Memory Computing (AIMC) is a promising paradigm sinceit performs matrix-vector multiplications, the critical kernel of many MLapplications, in-place in the analog domain within memory arrays structured ascrossbars of memory cells. However, several factors limit the full exploitationof this technology, including the physical fabrication of the crossbar devices,which constrain the memory capacity of a single array. Multi-AIMC architectureshave been proposed to overcome this limitation, but they have been demonstratedonly for tiny and custom CNNs or performing some layers off-chip. In this work,we present the full inference of an end-to-end ResNet-18 DNN on a 512-clusterheterogeneous architecture coupling a mix of AIMC cores and digital RISC-Vcores, achieving up to 20.2 TOPS. Moreover, we analyze the mapping of thenetwork on the available non-volatile cells, compare it with state-of-the-artmodels, and derive guidelines for next-generation many-core architectures basedon AIMC devices.

End-to-End DNN Inference on a Massively Parallel Analog In Memory Computing Architecture