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Power side-channel (PSC) attacks are well-known threats to sensitive hardwarelike advanced encryption standard (AES) crypto cores. Given the significantimpact of supply voltages (VCCs) on power profiles, various countermeasuresbased on VCC tuning have been proposed, among other defense strategies. Driverstrengths of cells, however, have been largely overlooked, despite havingdirect and significant impact on power profiles as well.  For the first time, we thoroughly explore the prospects of jointly tuningdriver strengths and VCCs as novel working principle for PSC-attackcountermeasures. Toward this end, we take the following steps: 1) we develop asimple circuit-level scheme for tuning; 2) we implement a CAD flow fordesign-time evaluation of ASICs, enabling security assessment of ICs beforetape-out; 3) we implement a correlation power analysis (CPA) framework forthorough and comparative security analysis; 4) we conduct an extensiveexperimental study of a regular AES design, implemented in ASIC as well as FPGAfabrics, under various tuning scenarios; 5) we summarize design guidelines forsecure and efficient joint tuning.  In our experiments, we observe that runtime tuning is more effective thanstatic tuning, for both ASIC and FPGA implementations. For the latter, the AEScore is rendered >11.8x (i.e., at least 11.8 times) as resilient as the untunedbaseline design. Layout overheads can be considered acceptable, with, e.g.,around +10% critical-path delay for the most resilient tuning scenario in FPGA.  We will release source codes for our methodology, as well as artifacts fromthe experimental study, post peer-review.

X-Volt: Joint Tuning of Driver Strengths and Supply Voltages Against Power Side-Channel Attacks