English (United Kingdom)

https://curated-unify.zendy.io/wp-json/zendy-region/v1/featured_content/oa?rat=en

https://curated-unify.zendy.io/wp-json/zendy-region/v1/highlighted_journal/

Global: Zendy Plus annual

Presents the access of premium content as premium feature

Premium Content

Presents the keyphrase highlighting as premium feature

Keyphrase Highlighting

Presents the summarisation as premium feature

Summarisation

Insights

Presents the pdf analysis as premium feature

PDF Analysis

Presents the zaia usage as premium feature

ZAIA

Global: Zendy Plus monthly

Global: Zendy Tools annual

Global: Zendy Tools monthly

Global: Zendy Free Plan

This thesis proposes novel ternary circuits aiming to reduce energy topreserve battery consumption. The proposed designs include eight ternary logicgates, three ternary combinational circuits, and six Ternary Arithmetic LogicUnits. This thesis applies the best tradeoff between reducing the number ofused transistors, utilizing energy efficient transistor arrangements such astransmission gates, and applying the dual supply voltages to achieve itsobjective. The proposed designs are compared to the latest ternary circuitsusing the HSPICE simulator for different supply voltages, differenttemperatures, and different frequencies. Simulations are performed to prove theefficiency of the proposed designs. The results demonstrate the advantage ofthe proposed designs with a reduction of over 73 percent in terms of transistorcount for the THA and over 88 percent in energy consumption for the STI, TNAND,TDecoder, TMUX, THA, and TMUL, respectively. Moreover, the noise immunity curveand Monte Carlo analysis for major process variations, TOX, CNT Diameter, CNTCount, and Channel length, were studied.

Multiple-Valued Logic Circuit Design and Data Transmission Intended for Embedded Systems