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Optimizing data movements is becoming one of the biggest challenges inheterogeneous computing to cope with data deluge and, consequently, big dataapplications. When creating specialized accelerators, modern high-levelsynthesis (HLS) tools are increasingly efficient in optimizing thecomputational aspects, but data transfers have not been adequately improved. Tocombat this, novel architectures such as High-Bandwidth Memory with wider databusses have been developed so that more data can be transferred in parallel.Designers must tailor their hardware/software interfaces to fully exploit theavailable bandwidth. HLS tools can automate this process, but the designer mustfollow strict coding-style rules. If the bus width is not evenly divisible bythe data width (e.g., when using custom-precision data types) or if the arraysare not power-of-two length, the HLS-generated accelerator will likely notfully utilize the available bandwidth, demanding even more manual effort fromthe designer. We propose a methodology to automatically find and implement adata layout that, when streamed between memory and an accelerator, uses ahigher percentage of the available bandwidth than a naive or HLS-optimizeddesign. We borrow concepts from multiprocessor scheduling to achieve such highefficiency.

Iris: Automatic Generation of Efficient Data Layouts for High Bandwidth Utilization