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Persistent memory (pmem) products bring the persistence domain up to thememory level. Intel recently introduced the eADR feature that guarantees toflush data buffered in CPU cache to pmem on a power outage, thereby making theCPU cache a transient persistence domain. Researchers have explored how toenable the atomic durability for applications' in-pmem data. In this paper, weexploit the eADR-supported CPU cache to do so. A modified cache line, untilwritten back to pmem, is a natural redo log copy of the in-pmem data. However,a write-back due to cache replacement or eADR on a crash overwrites theoriginal copy. We accordingly develop Hercules, a hardware logging design forthe transaction-level atomic durability, with supportive components installedin CPU cache, memory controller (MC), and pmem. When a transaction commits,Hercules commits on-chip its data staying in cache lines. For cache linesevicted before the commit, Hercules asks the MC to redirect and persist theminto in-pmem log entries and commits them off-chip upon committing thetransaction. Hercules lazily conducts pmem writes only for cache replacementsat runtime. On a crash, Hercules saves metadata and data for activetransactions into pmem for recovery. Experiments show that, by using CPU cachefor both buffering and logging, Hercules yields much higher throughput andincurs significantly fewer pmem writes than state-of-the-art designs.

Enabling Atomic Durability for Persistent Memory with Transiently Persistent CPU Cache