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A growing number of applications like probabilistic machine learning, sparselinear algebra, robotic navigation, etc., exhibit irregular data flowcomputation that can be modeled with directed acyclic graphs (DAGs). Theirregularity arises from the seemingly random connections of nodes, which makesthe DAG structure unsuitable for vectorization on CPU or GPU. Moreover, thenodes usually represent a small number of arithmetic operations that cannotamortize the overhead of launching tasks/kernels for each node, further posingchallenges for parallel execution.  To enable energy-efficient execution, this work proposes DAG processing unit(DPU) version 2, a specialized processor architecture optimized for irregularDAGs with static connectivity. It consists of a tree-structured datapath forefficient data reuse, a customized banked register file, and interconnectstuned to support irregular register accesses. DPU-v2 is utilized effectivelythrough a targeted compiler that systematically maps operations to thedatapath, minimizes register bank conflicts, and avoids pipeline hazards.Finally, a design space exploration identifies the optimal architectureconfiguration that minimizes the energy-delay product. This hardware-softwareco-optimization approach results in a speedup of 1.4$\times$, 3.5$\times$, and14$\times$ over a state-of-the-art DAG processor ASIP, a CPU, and a GPU,respectively, while also achieving a lower energy-delay product. In this way,this work takes an important step toward enabling an embedded execution ofemerging DAG workloads.

DPU-v2: Energy-efficient execution of irregular directed acyclic graphs