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SNNs are an active research domain towards energy efficient machineintelligence. Compared to conventional ANNs, SNNs use temporal spike data andbio-plausible neuronal activation functions such as Leaky-IntegrateFire/Integrate Fire (LIF/IF) for data processing. However, SNNs incursignificant dot-product operations causing high memory and computation overheadin standard von-Neumann computing platforms. Today, In-Memory Computing (IMC)architectures have been proposed to alleviate the "memory-wall bottleneck"prevalent in von-Neumann architectures. Although recent works have proposedIMC-based SNN hardware accelerators, the following have been overlooked- 1) theadverse effects of crossbar non-ideality on SNN performance due to repeatedanalog dot-product operations over multiple time-steps, 2) hardware overheadsof essential SNN-specific components such as the LIF/IF and data communicationmodules. To this end, we propose SpikeSim, a tool that can perform realisticperformance, energy, latency and area evaluation of IMC-mapped SNNs. SpikeSimconsists of a practical monolithic IMC architecture called SpikeFlow formapping SNNs. Additionally, the non-ideality computation engine (NICE) andenergy-latency-area (ELA) engine performs hardware-realistic evaluation ofSpikeFlow-mapped SNNs. Based on 65nm CMOS implementation and experiments onCIFAR10, CIFAR100 and TinyImagenet datasets, we find that the LIF/IF neuronalmodule has significant area contribution (>11% of the total hardware area). Wepropose SNN topological modifications leading to 1.24x and 10x reduction in theneuronal module's area and the overall energy-delay-product value,respectively. Furthermore, in this work, we perform a holistic comparisonbetween IMC implemented ANN and SNNs and conclude that lower number oftime-steps are the key to achieve higher throughput and energy-efficiency forSNNs compared to 4-bit ANNs.

SpikeSim: An end-to-end Compute-in-Memory Hardware Evaluation Tool for Benchmarking Spiking Neural Networks