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The recently proposed recursive projection-aggregation (RPA) decodingalgorithm for Reed-Muller codes has received significant attention as itprovides near-ML decoding performance at reasonable complexity for short codes.However, its complicated structure makes it unsuitable for hardwareimplementation. Iterative projection-aggregation (IPA) decoding is a modifiedversion of RPA decoding that simplifies the hardware implementation. In thiswork, we present a flexible hardware architecture for the IPA decoder that canbe configured from fully-sequential to fully-parallel, thus making it suitablefor a wide range of applications with different constraints and resourcebudgets. Our simulation and implementation results show that the IPA decoderhas 41% lower area consumption, 44% lower latency, four times higherthroughput, but currently seven times higher power consumption for a code withblock length of 128 and information length of 29 compared to a state-of-the-artpolar successive cancellation list (SCL) decoder with comparable decodingperformance.

Pipelined Architecture for Soft-decision Iterative Projection Aggregation Decoding for RM Codes