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On modern field-programmable gate arrays (FPGAs), certain critical pathportions of the designs might be prearranged into many multi-cell macros duringsynthesis. These movable macros with constraints of shape and resources lead tochallenging mixed-size placement for FPGA designs which cannot be addressed byprevious analytical placers. Moreover, general timing-driven placementalgorithms are facing challenges when handling real-world application designand ultrascale FPGA architectures. In this work, we propose AMF-Placer 2.0, anopen-source comprehensive timing-driven analytical mixed-size FPGA placer. Itsupports mixed-size placement of heterogeneous resources (e.g.,LUT/FF/LUTRAM/MUX/CARRY/DSP/BRAM) on FPGA, with an interface to Xilinx Vivado.Standing upon the shoulders of AMF-Placer 1.0, AMFPlacer 2.0 is equipped with aseries of new techniques for timing optimization, including a simple buteffective timing model, placement-blockage-aware anchor insertion, WNS-awaretiming-driven quadratic placement, and sector-guided detailed placement. Basedon a set of the latest large open-source benchmarks from various domains forXilinx Ultrascale FPGAs, experimental results indicate that critical pathdelays realized by AMF-Placer 2.0 are averagely 2.2% and 0.59% higher thanthose achieved by commercial tool Xilinx Vivavo 2020.2 and 2021.2 respectively.Meanwhile, the average runtime of placement procedure of AMF-Placer 2.0 is 14%and 8.5% higher than Xilinx Vivavo 2020.2 and 2021.2 respectively. Althoughlimited by the absence of the exact timing model of the device, the informationof design hierarchy and accurate routing feedback, AMF-Placer 2.0 is the firstopen-source FPGA placer which can handle the timingdriven mixed-size placementof practical complex designs with various FPGA resources and achieves thecomparable quality to the latest commercial tools.

AMF-Placer 2.0: Open Source Timing-driven Analytical Mixed-size Placer for Large-scale Heterogeneous FPGA