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Recent nano-technological advances enable the Monolithic 3D (M3D) integrationof multiple memory and logic layers in a single chip with fine-grainedconnections. M3D technology leads to significantly higher main memory bandwidthand shorter latency than existing 3D-stacked systems. We show for a variety ofworkloads on a state-of-the-art M3D system that the performance and energybottlenecks shift from the main memory to the core and cache hierarchy. Hence,there is a need to revisit current core and cache designs that have beenconventionally tailored to tackle the memory bottleneck.  Our goal is to redesign the core and cache hierarchy, given the fundamentallynew trade-offs of M3D, to benefit a wide range of workloads. To this end, wetake two steps. First, we perform a design space exploration of the cache andcore's key components. We highlight that in M3D systems, (i) removing theshared last-level cache leads to similar or larger performance benefits thanincreasing its size or reducing its latency; (ii) improving L1 latency has alarge impact on improving performance; (iii) wider pipelines are increasinglybeneficial; (iv) the performance impact of branch speculation and pipelinefrontend increases; (v) the current synchronization schemes limit parallelspeedup. Second, we propose an optimized M3D system, RevaMp3D, where (i) usingthe tight connectivity between logic layers, we efficiently increase pipelinewidth, reduce L1 latency, and enable fine-grained synchronization; (ii) usingthe high-bandwidth and energy-efficient main memory, we alleviate the amplifiedenergy and speculation bottlenecks by memoizing the repetitive fetched,decoded, and reordered instructions and turning off the relevant parts of thecore pipeline when possible. RevaMp3D provides, on average, 81% speedup, 35%energy reduction, and 12.3% smaller area compared to the baseline M3D system.

RevaMp3D: Architecting the Processor Core and Cache Hierarchy for Systems with Monolithically-Integrated Logic and Memory