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Electronic control systems used for quantum computing have becomeincreasingly complex as multiple qubit technologies employ larger numbers ofqubits with higher fidelity targets. Whereas the control systems for differenttechnologies share some similarities, parameters like pulse duration,throughput, real-time feedback, and latency requirements vary widely dependingon the qubit type. In this paper, we evaluate the performance of modernSystem-on-Chip (SoC) architectures in meeting the control demands associatedwith performing quantum gates on trapped-ion qubits, particularly focusing oncommunication within the SoC. A principal focus of this paper is the datatransfer latency and throughput of several high-speed on-chip mechanisms onXilinx multi-processor SoCs, including those that utilize direct memory access(DMA). They are measured and evaluated to determine an upper bound on the timerequired to reconfigure a gate parameter. Worst-case and average-case bandwidthrequirements for a custom gate sequencer core are compared with theexperimental results. The lowest-variability, highest-throughput data-transfermechanism is DMA between the real-time processing unit (RPU) and the PL, wherebandwidths up to 19.2 GB/s are possible. For context, this enablesreconfiguration of qubit gates in less than 2$\mu$s, comparable to the fastestgate time. Though this paper focuses on trapped-ion control systems, the gateabstraction scheme and measured communication rates are applicable to a broadrange of quantum computing technologies.

Design and analysis of digital communication within an SoC-based control system for trapped-ion quantum computing