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DRAM is the building block of modern main memory systems. DRAM cells must beperiodically refreshed to prevent data loss. Refresh operations degrade systemperformance by interfering with memory accesses. As DRAM chip density increaseswith technology node scaling, refresh operations also increase because: 1) thenumber of DRAM rows in a chip increases; and 2) DRAM cells need additionalrefresh operations to mitigate bit failures caused by RowHammer, a failuremechanism that becomes worse with technology node scaling. Thus, it is criticalto enable refresh operations at low performance overhead. To this end, wepropose a new operation, Hidden Row Activation (HiRA), and the HiRA MemoryController (HiRA-MC).  HiRA hides a refresh operation's latency by refreshing a row concurrentlywith accessing or refreshing another row within the same bank. Unlike priorworks, HiRA achieves this parallelism without any modifications tooff-the-shelf DRAM chips. To do so, it leverages the new observation that tworows in the same bank can be activated without data loss if the rows areconnected to different charge restoration circuitry. We experimentallydemonstrate on 56% real off-the-shelf DRAM chips that HiRA can reliablyparallelize a DRAM row's refresh operation with refresh or activation of any ofthe 32% of the rows within the same bank. By doing so, HiRA reduces the overalllatency of two refresh operations by 51.4%.  HiRA-MC modifies the memory request scheduler to perform HiRA when a refreshoperation can be performed concurrently with a memory access or anotherrefresh. Our system-level evaluations show that HiRA-MC increases systemperformance by 12.6% and 3.73x as it reduces the performance degradation due toperiodic refreshes and refreshes for RowHammer protection (preventiverefreshes), respectively, for future DRAM chips with increased density andRowHammer vulnerability.

HiRA: Hidden Row Activation for Reducing Refresh Latency of Off-the-Shelf DRAM Chips