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Valley-spin hall (VSH) effect in monolayer WSe2 has been shown to exhibithighly beneficial features for nonvolatile memory (NVM) design. Key advantagesof VSH-based magnetic random-access memory (VSH-MRAM) over spin orbit torque(SOT)-MRAM include access transistor-less compact bit-cell and low powerswitching of perpendicular magnetic anisotropy (PMA) magnets. Nevertheless,large device resistance in the read path (RS) due to low mobility of WSe2 andSchottky contacts deteriorates sense margin, offsetting the benefits ofVSH-MRAM. To address this limitation, we propose another flavor of VSH-basedMRAM that (while inheriting most of the benefits of VSH-MRAM) achieves lower RSin the read path by electrically isolating the read and write terminals. Thisis enabled by coupling VSH with electrically-isolated but magnetically-coupledPMA magnets via interlayer exchange-coupling. Designing the proposed devicesusing object oriented micro magnetic framework (OOMMF) simulation, we ensurethe robustness of the exchange-coupled PMA system under process variations. Tomaintain a compact memory footprint, we share the read access transistor acrossmultiple bit-cells. Compared to the existing VSH-MRAMs, our design achieves39%-42% and 36%-46% reduction in read time and energy, respectively, along with1.1X-1.3X larger sense margin at a comparable area. This comes at the cost of1.7X and 2.0X increase in write time and energy, respectively. Thus, theproposed design is suitable for applications in which reads are more dominantthan writes.

Valley-Spin Hall Effect-based Nonvolatile Memory with Exchange-Coupling-Enabled Electrical Isolation of Read and Write Paths